1. Field of the Invention
The invention relates to a semiconductor device and a manufacturing method thereof, particularly, a semiconductor device having a penetrating electrode and a manufacturing method thereof.
2. Description of the Related Art
CSP (Chip Size Package) has received attention in recent years as a three-dimensional mounting technology as well as a new packaging technology. The CSP means a small package having almost the same outside dimensions as those of a semiconductor die packaged in it.
Conventionally, BGA (Ball Grid Array) type semiconductor devices having penetrating electrodes have been known as a kind of CSP. This BGA type semiconductor device has a penetrating electrode penetrating a semiconductor substrate and connected with a pad electrode. In this BGA type semiconductor device, a plurality of ball-shaped conductive terminals made of metal such as solder is arrayed in a grid pattern on a back surface of the device.
When this semiconductor device is mounted on electronic equipment, the ball-shaped conductive terminals are connected to wiring patterns on a circuit board (e.g. printed board).
Such a BGA type semiconductor device has advantages in providing a large number of conductive terminals and in reducing size over other CSP type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package), which have lead pins protruding from their sides.
Next, a conventional manufacturing method of the BGA-type semiconductor device having the penetrating electrode will briefly described. First, on a front surface of a semiconductor substrate formed with a pad electrode with a first insulation film therebetween, a supporting body is attached with a resin layer therebetween. The attachment of this supporting body is performed according to needs, and not necessarily performed.
Next, a via hole is formed from a back surface of the semiconductor substrate to the pad electrode by etching the semiconductor substrate. Furthermore, a second insulation film is formed on the back surface of the semiconductor substrate including in the via hole, exposing the pad electrode at a bottom of the via hole.
Furthermore, a penetrating electrode is formed on the second insulation film in the via hole, being electrically connected with the pad electrode exposed at the bottom. At the same time as this, a wiring layer is formed on the second insulation film on the back surface of the semiconductor substrate, being connected with the penetrating electrode. Then, a protection layer is formed on the back surface of the semiconductor substrate including on the wiring layer.
Furthermore, a part of the protection layer may be opened to expose a part of the wiring layer, and a conductive terminal may be formed on this wiring layer. Then, the semiconductor substrate is cut and separated into a plurality of semiconductor dies by dicing. The relevant technology is disclosed in the Japanese Patent Application Publication No. 2003-309221.
Next, the above-described conventional semiconductor device manufacturing method will be partially described with reference to figures. FIGS. 11 and 12 are cross-sectional views showing the conventional semiconductor device manufacturing method.
In the conventional semiconductor device, as shown in FIG. 11, a pad electrode 52 is formed on a front surface of a semiconductor substrate 50 with an insulation film 51 therebetween in so-called front-end processes. Furthermore, in subsequent processes, a supporting body 54 is attached on the front surface of the semiconductor substrate 50 formed with the pad electrode 52 with a resin layer 53 therebetween. Thermal stresses (called residual stress or intrinsic stress) are likely to be generated in the pad electrode 52 when the pad electrode 52 is deposited.
However, as shown in FIG. 12, when the semiconductor substrate 50 is etched using the resist layer 55 as a mask to form a via hole 56 penetrating the semiconductor substrate 50, the pad electrode 52 at a bottom of the via hole 56 is deformed, projecting into the via hole 56, although it should be flat.
This deformation of the pad electrode 52 is caused by that the stress accumulated in the pad electrode 52 when the pad electrode 52 is deposited in the front-end processes loses its balance by a thermal load in a thermal cycle test and so on, and thus the stress is concentrated in the pad electrode 52 at the bottom of the via hole 56 so as to be released therefrom. Furthermore, the deformation also occurs after the insulation film 51 is etched.
Furthermore, after a penetrating electrode (not shown) formed of, for example, copper (Cu) is formed, being connected with the pad electrode 52 at the bottom of the via hole 56, the pad electrode 52 is deformed projecting on the back surface side of the semiconductor substrate 50 like being pulled by the penetrating electrode. This deformation is caused by a relation between residual stress accumulated in the penetrating electrode when the penetrating electrode is formed and the stress accumulated in the pad electrode 52.
Furthermore, the deformation of the pad electrode 52 described above sometimes causes damage or disconnection in the pad electrode 52 by metal fatigue. Therefore, after the penetrating electrode (not shown) formed of, for example, copper (Cu) is formed in the via hole 56 including on the deformed pad electrode 52, there sometimes occurs connection failure between the penetrating electrode and the pad electrode exposed in the via hole 56. That is, the deformation of the pad electrode 52 causes a problem of decreasing the reliability of the semiconductor device having the penetrating electrode. As a result, the reliability and yield of the semiconductor device having the penetrating electrode decreases.